While many venture firms seem to only have eyes for AI these days, Nexus Venture Partners is deliberately splitting its focus for its new $700 million fund.
The firm will back AI startups and seek out India-focused startups in consumer, fintech, and digital infrastructure.
AI has soaked up most of the venture capital raised globally and the 20-year-old VC firm also sees AI as a defining technological shift. But it argues crowding into a single, overheated category carries its own risks. India’s digital economy provides a counterbalance: an expanding market where AI adoption is rising and opportunities remain more diverse.
For Nexus, that balance is rooted in its origins. The Delaware-headquartered firm, with offices in Menlo Park, Mumbai and Bengaluru, has operated as a single fund and an integrated U.S.–India team since its founding in 2006.
It backs early-stage software and India-focused startups from the same pool of capital. Over time, its cross-border software bets have encompassed a range from infrastructure and developer tools to AI agent startups. U.S. portfolio includes companies such as Postman, Apollo, MinIO, Giga, and Firecrawl, which have become widely adopted in developer tooling and AI infrastructure.
Meanwhile its India portfolio has broadened across consumer, fintech, logistics, and digital infrastructure. Some of its bets there include Zepto, Delhivery, Rapido, Turtlemint, and Infra.Market
“AI is a huge inflection point, and we are anchoring on that,” Jishnu Bhattacharjee, a managing partner at Nexus Venture Partners in the U.S., told TechCrunch in an interview. “But we are also seeing that many of these AI innovations are actually getting used to serve the masses better.”
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Nexus manages $3.2 billion in capital across its funds and has invested in more than 130 companies over the years. The firm has recorded more than 30 exits to date, including several IPOs, underscoring the depth of its early-stage, long-horizon approach.
Abhishek Sharma, a managing partner at Nexus Venture Partners in the U.S., told TechCrunch the firm’s sweet spot remains inception to seed and Series A, often beginning with checks as small as a few hundred thousand dollars or around $1 million.
Nexus, which operates with an eight-member investment team, began with a $100 million fund and has kept its fund size at $700 million since launching Fund VII in 2023. It typically raises every 2.5 to 3 years. Bhattacharjee said the reason for keeping the eighth fund the same size was the firm believes $700 million is the right amount for its early-stage strategy.
“We don’t want to raise money for the sake of raising,” he noted.
Even though India’s AI journey is not as advanced as the U.S.’s in many areas, Nexus believes India could leapfrog in several parts of the AI ecosystem.
Bhattacharjee underlined the country’s large talent pool, rising digital infrastructure, and demand for localized models that support India’s many languages and service needs. These dynamics, he said, are pushing Indian startups to build AI applications and agents faster, often atop open-source tools and emerging domestic AI infrastructure companies.
The partners pointed to companies backed by Nexus, such as Zepto and Neysa, to illustrate how AI is taking shape in India. They said Zepto, the quick-commerce platform, uses AI extensively across its operations — from customer support to routing and fulfillment — demonstrating how consumer businesses are becoming deeply AI-native. Besides, infrastructure players like Neysa are emerging to address India-specific needs, including sovereign AI workloads, localized data handling and support for the country’s many languages.
Nexus did not share fund metrics. The partners said its funds have been realizing significant enough returns over the years to largely fill this fund from returning limited partners. The firm’s LP base spans the U.S., Europe, the Middle East, Southeast Asia and Japan.
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![IBM Crosses One of Computing’s Biggest Barriers With World’s First Sub-1 Nanometer Chip
In a major breakthrough, IBM revealed the world’s first semiconductor chip technology built on a sub-1 nanometer chipmaking process. For comparison, the process uses transistor features smaller than the width of a DNA strand, which measures about 2.5 nanometers across. The chip itself is about the size of a fingernail but holds almost 100 billion transistors, and the company expects it could enter markets as early as the next five years. In a statement released today, IBM said the new chip features nearly twice the density of its 2-nanometer chip, released in 2021. According to an accompanying technical report, the chip also demonstrated up to 70% greater energy efficiency than its predecessor. In designing the chip, researchers developed an “entirely new transistor architecture” called nanostack, which “vertically stacks and staggers transistors” to enable IBM’s 0.7-nanometer chip technology, IBM explained. A section of the chip seen with a transmission electron microscope. Credit: IBM “With our new nanostack architecture, we’re not just making smaller transistors,” Jay Gambetta, director of IBM Research, said in the statement. “We’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
Smaller and smaller Semiconductor chips enable things like computers, home appliances, communications, and transportation devices. In 1965, Intel co-founder Gordon Moore surmised that transistor capacities evolved at a predictable and consistent rate. Specifically, all things considered, the number of transistors on a semiconductor chip would double about every two years. For a while, the so-called Moore’s Law held rather well—until, that is, things hit a literal wall.
“Moore’s Law was never meant to last forever,” according to a blog post by the Massachusetts Institute of Technology’s (MIT) Computer Science and Artificial Intelligence Lab. “Transistors can only get so small and, eventually, the more permanent laws of physics get in the way.” That is, as companies try to cram more transistors into smaller chips, new advances in transistor technology take longer than two years, so Moore’s Law has been over since at least 2016, Charles Leiserson, a computer scientist at MIT, said in the blog. Accordingly, the issue now is to consider how improvements in chip performance fit into a longer-term picture, Willy Shih, an economist at Harvard Business School, said in an explainer.
Reaching atomic levels In that sense, IBM’s latest chip represents an inventive approach for bypassing the limits of physical scaling. Specifically, two wafers with nanosheet-style transistors are glued together like a sandwich to vertically stack two layers of transistors, and related technical assessments suggested that the wafer stacking was flexible and scalable enough to support real computation, Huiming Bu, vice president of IBM’s silicon technology research team, said in a press briefing on the chip. Researcher holding IBM’s sub-1 nm node wafer. Credit: IBM That said, this chip isn’t quite ready for manufacturing just yet. The company’s goal is to enter production in the next five years, but there’s still work to be done. For instance, Bu pointed out that the team was still working on pathways to prevent thermal noise or integration into existing systems in the high-performance computing community. “From my perspective, I hope to see it be as successful as the 2-nanometer [chip] and become the industry platform,” Gambetta said during the briefing. “And as we see with AI and classical computing in general, we are only seeing more and more consumption.” #IBM #Crosses #Computings #Biggest #Barriers #Worlds #Sub1 #Nanometer #ChipIBM,Semiconductors,transistors](https://gizmodo.com/app/uploads/2026/06/nanostacking-ibm-sub-nm-chip-1280x720.jpg "IBM Crosses One of Computing’s Biggest Barriers With World’s First Sub-1 Nanometer Chip
In a major breakthrough, IBM revealed the world’s first semiconductor chip technology built on a sub-1 nanometer chipmaking process. For comparison, the process uses transistor features smaller than the width of a DNA strand, which measures about 2.5 nanometers across. The chip itself is about the size of a fingernail but holds almost 100 billion transistors, and the company expects it could enter markets as early as the next five years. In a statement released today, IBM said the new chip features nearly twice the density of its 2-nanometer chip, released in 2021. According to an accompanying technical report, the chip also demonstrated up to 70% greater energy efficiency than its predecessor. In designing the chip, researchers developed an “entirely new transistor architecture” called nanostack, which “vertically stacks and staggers transistors” to enable IBM’s 0.7-nanometer chip technology, IBM explained. A section of the chip seen with a transmission electron microscope. Credit: IBM “With our new nanostack architecture, we’re not just making smaller transistors,” Jay Gambetta, director of IBM Research, said in the statement. “We’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
Smaller and smaller Semiconductor chips enable things like computers, home appliances, communications, and transportation devices. In 1965, Intel co-founder Gordon Moore surmised that transistor capacities evolved at a predictable and consistent rate. Specifically, all things considered, the number of transistors on a semiconductor chip would double about every two years. For a while, the so-called Moore’s Law held rather well—until, that is, things hit a literal wall.
“Moore’s Law was never meant to last forever,” according to a blog post by the Massachusetts Institute of Technology’s (MIT) Computer Science and Artificial Intelligence Lab. “Transistors can only get so small and, eventually, the more permanent laws of physics get in the way.” That is, as companies try to cram more transistors into smaller chips, new advances in transistor technology take longer than two years, so Moore’s Law has been over since at least 2016, Charles Leiserson, a computer scientist at MIT, said in the blog. Accordingly, the issue now is to consider how improvements in chip performance fit into a longer-term picture, Willy Shih, an economist at Harvard Business School, said in an explainer.
Reaching atomic levels In that sense, IBM’s latest chip represents an inventive approach for bypassing the limits of physical scaling. Specifically, two wafers with nanosheet-style transistors are glued together like a sandwich to vertically stack two layers of transistors, and related technical assessments suggested that the wafer stacking was flexible and scalable enough to support real computation, Huiming Bu, vice president of IBM’s silicon technology research team, said in a press briefing on the chip. Researcher holding IBM’s sub-1 nm node wafer. Credit: IBM That said, this chip isn’t quite ready for manufacturing just yet. The company’s goal is to enter production in the next five years, but there’s still work to be done. For instance, Bu pointed out that the team was still working on pathways to prevent thermal noise or integration into existing systems in the high-performance computing community. “From my perspective, I hope to see it be as successful as the 2-nanometer [chip] and become the industry platform,” Gambetta said during the briefing. “And as we see with AI and classical computing in general, we are only seeing more and more consumption.” #IBM #Crosses #Computings #Biggest #Barriers #Worlds #Sub1 #Nanometer #ChipIBM,Semiconductors,transistors")
![IBM Crosses One of Computing’s Biggest Barriers With World’s First Sub-1 Nanometer Chip
In a major breakthrough, IBM revealed the world’s first semiconductor chip technology built on a sub-1 nanometer chipmaking process. For comparison, the process uses transistor features smaller than the width of a DNA strand, which measures about 2.5 nanometers across. The chip itself is about the size of a fingernail but holds almost 100 billion transistors, and the company expects it could enter markets as early as the next five years. In a statement released today, IBM said the new chip features nearly twice the density of its 2-nanometer chip, released in 2021. According to an accompanying technical report, the chip also demonstrated up to 70% greater energy efficiency than its predecessor. In designing the chip, researchers developed an “entirely new transistor architecture” called nanostack, which “vertically stacks and staggers transistors” to enable IBM’s 0.7-nanometer chip technology, IBM explained. A section of the chip seen with a transmission electron microscope. Credit: IBM “With our new nanostack architecture, we’re not just making smaller transistors,” Jay Gambetta, director of IBM Research, said in the statement. “We’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
Smaller and smaller Semiconductor chips enable things like computers, home appliances, communications, and transportation devices. In 1965, Intel co-founder Gordon Moore surmised that transistor capacities evolved at a predictable and consistent rate. Specifically, all things considered, the number of transistors on a semiconductor chip would double about every two years. For a while, the so-called Moore’s Law held rather well—until, that is, things hit a literal wall.
“Moore’s Law was never meant to last forever,” according to a blog post by the Massachusetts Institute of Technology’s (MIT) Computer Science and Artificial Intelligence Lab. “Transistors can only get so small and, eventually, the more permanent laws of physics get in the way.” That is, as companies try to cram more transistors into smaller chips, new advances in transistor technology take longer than two years, so Moore’s Law has been over since at least 2016, Charles Leiserson, a computer scientist at MIT, said in the blog. Accordingly, the issue now is to consider how improvements in chip performance fit into a longer-term picture, Willy Shih, an economist at Harvard Business School, said in an explainer.
Reaching atomic levels In that sense, IBM’s latest chip represents an inventive approach for bypassing the limits of physical scaling. Specifically, two wafers with nanosheet-style transistors are glued together like a sandwich to vertically stack two layers of transistors, and related technical assessments suggested that the wafer stacking was flexible and scalable enough to support real computation, Huiming Bu, vice president of IBM’s silicon technology research team, said in a press briefing on the chip. Researcher holding IBM’s sub-1 nm node wafer. Credit: IBM That said, this chip isn’t quite ready for manufacturing just yet. The company’s goal is to enter production in the next five years, but there’s still work to be done. For instance, Bu pointed out that the team was still working on pathways to prevent thermal noise or integration into existing systems in the high-performance computing community. “From my perspective, I hope to see it be as successful as the 2-nanometer [chip] and become the industry platform,” Gambetta said during the briefing. “And as we see with AI and classical computing in general, we are only seeing more and more consumption.” #IBM #Crosses #Computings #Biggest #Barriers #Worlds #Sub1 #Nanometer #ChipIBM,Semiconductors,transistors](https://i1.wp.com/gizmodo.com/app/uploads/2026/06/nanostacking-ibm-sub-nm-chip-1280x720.jpg?ssl=1 "IBM Crosses One of Computing’s Biggest Barriers With World’s First Sub-1 Nanometer Chip
In a major breakthrough, IBM revealed the world’s first semiconductor chip technology built on a sub-1 nanometer chipmaking process. For comparison, the process uses transistor features smaller than the width of a DNA strand, which measures about 2.5 nanometers across. The chip itself is about the size of a fingernail but holds almost 100 billion transistors, and the company expects it could enter markets as early as the next five years. In a statement released today, IBM said the new chip features nearly twice the density of its 2-nanometer chip, released in 2021. According to an accompanying technical report, the chip also demonstrated up to 70% greater energy efficiency than its predecessor. In designing the chip, researchers developed an “entirely new transistor architecture” called nanostack, which “vertically stacks and staggers transistors” to enable IBM’s 0.7-nanometer chip technology, IBM explained. A section of the chip seen with a transmission electron microscope. Credit: IBM “With our new nanostack architecture, we’re not just making smaller transistors,” Jay Gambetta, director of IBM Research, said in the statement. “We’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
Smaller and smaller Semiconductor chips enable things like computers, home appliances, communications, and transportation devices. In 1965, Intel co-founder Gordon Moore surmised that transistor capacities evolved at a predictable and consistent rate. Specifically, all things considered, the number of transistors on a semiconductor chip would double about every two years. For a while, the so-called Moore’s Law held rather well—until, that is, things hit a literal wall.
“Moore’s Law was never meant to last forever,” according to a blog post by the Massachusetts Institute of Technology’s (MIT) Computer Science and Artificial Intelligence Lab. “Transistors can only get so small and, eventually, the more permanent laws of physics get in the way.” That is, as companies try to cram more transistors into smaller chips, new advances in transistor technology take longer than two years, so Moore’s Law has been over since at least 2016, Charles Leiserson, a computer scientist at MIT, said in the blog. Accordingly, the issue now is to consider how improvements in chip performance fit into a longer-term picture, Willy Shih, an economist at Harvard Business School, said in an explainer.
Reaching atomic levels In that sense, IBM’s latest chip represents an inventive approach for bypassing the limits of physical scaling. Specifically, two wafers with nanosheet-style transistors are glued together like a sandwich to vertically stack two layers of transistors, and related technical assessments suggested that the wafer stacking was flexible and scalable enough to support real computation, Huiming Bu, vice president of IBM’s silicon technology research team, said in a press briefing on the chip. Researcher holding IBM’s sub-1 nm node wafer. Credit: IBM That said, this chip isn’t quite ready for manufacturing just yet. The company’s goal is to enter production in the next five years, but there’s still work to be done. For instance, Bu pointed out that the team was still working on pathways to prevent thermal noise or integration into existing systems in the high-performance computing community. “From my perspective, I hope to see it be as successful as the 2-nanometer [chip] and become the industry platform,” Gambetta said during the briefing. “And as we see with AI and classical computing in general, we are only seeing more and more consumption.” #IBM #Crosses #Computings #Biggest #Barriers #Worlds #Sub1 #Nanometer #ChipIBM,Semiconductors,transistors")
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