If there’s one thing that VCs agree on when backing AI startups, it’s that AI requires a different investment approach than prior technological shifts.
“It’s a funky time,” said Aileen Lee, founder and managing partner of Cowboy Ventures, onstage at TechCrunch Disrupt 2025. The longtime VC noted that the rules of investing have significantly shifted now that some AI companies are leaping from “zero to $100 million in revenue in a single year.”
However, Lee also noted that, based on her firm’s research, Series A investors aren’t just seeking rapid revenue growth. “It’s an algorithm with different variables and different coefficients.”
Some of the factors investors now measure, according to Lee, include whether the startup is generating data, the strength of its competitive moat, the founders’ past accomplishments, and the technical depth of the product. “Depending on what your company is, the output of the algorithmic formula is going to be different,” she said.
Jon McNeill, co-founder and CEO of startup creation firm DVx Ventures, stated that even startups that grow rapidly from inception to $5 million in revenue often struggle to secure follow-on funding. “I think this game has changed, and it is changing dynamically,” he said.
McNeill noted that Series A investors are now applying the same rigorous standards to seed-stage startups that they previously reserved for more mature companies.
“I think a lot of investors have figured out that the breakout companies, in most cases, don’t have the best tech,” McNeill said about why Series A VCs are looking so closely at startups’ ability to attract and retain customers. “They have the best go-to market.”
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Steve Jang, founder and managing partner of Kindred Ventures, disagreed that a strong go-to-market (GTM), an industry term for sales and marketing, holds greater weight for investors. “I don’t think it’s 100% true to say mediocre technology, great GTM wins and raises money and gets customers. I think that it’s a necessary requirement to have both.”
While McNeill later clarified that having a solid product is important, he indicated that his initial comment was related to the founders’ need to develop an exceptionally strong sales and marketing strategy right out of the gate. “Investors are getting much more sophisticated on the go-to market than they have in the past,” he said.
(The debate over marketing versus tech was brought to the forefront later during the conference when Roy Lee, founder of the viral startup Cluely, said onstage that launching a product that barely worked, even with massive social media fame, may not always be the best idea.)
Aileen Lee added that AI startups are now under pressure to deliver product updates and new features at an unprecedented pace, preempting existing companies that might try to introduce similar products. “If you look at how much OpenAI and Anthropic are shipping, you’re going to have to figure out how to match how much you ship, how quickly and the quality of it,” she said.
Despite the expectations for breakneck growth and fast product development, panelists agreed that the AI industry is still in its very early stages. As Jang put it, “There are no clear, outright winners, even in LLMs. There are competitors nipping at their heels.”
This means startups still have a path to unseating perceived leaders, whether they are decades-old companies or fast-moving newcomers.
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#VCs #abandon #rules #funky #time #investing #startups #TechCrunch
![IBM Crosses One of Computing’s Biggest Barriers With World’s First Sub-1 Nanometer Chip
In a major breakthrough, IBM revealed the world’s first semiconductor chip technology built on a sub-1 nanometer chipmaking process. For comparison, the process uses transistor features smaller than the width of a DNA strand, which measures about 2.5 nanometers across. The chip itself is about the size of a fingernail but holds almost 100 billion transistors, and the company expects it could enter markets as early as the next five years. In a statement released today, IBM said the new chip features nearly twice the density of its 2-nanometer chip, released in 2021. According to an accompanying technical report, the chip also demonstrated up to 70% greater energy efficiency than its predecessor. In designing the chip, researchers developed an “entirely new transistor architecture” called nanostack, which “vertically stacks and staggers transistors” to enable IBM’s 0.7-nanometer chip technology, IBM explained. A section of the chip seen with a transmission electron microscope. Credit: IBM “With our new nanostack architecture, we’re not just making smaller transistors,” Jay Gambetta, director of IBM Research, said in the statement. “We’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
Smaller and smaller Semiconductor chips enable things like computers, home appliances, communications, and transportation devices. In 1965, Intel co-founder Gordon Moore surmised that transistor capacities evolved at a predictable and consistent rate. Specifically, all things considered, the number of transistors on a semiconductor chip would double about every two years. For a while, the so-called Moore’s Law held rather well—until, that is, things hit a literal wall.
“Moore’s Law was never meant to last forever,” according to a blog post by the Massachusetts Institute of Technology’s (MIT) Computer Science and Artificial Intelligence Lab. “Transistors can only get so small and, eventually, the more permanent laws of physics get in the way.” That is, as companies try to cram more transistors into smaller chips, new advances in transistor technology take longer than two years, so Moore’s Law has been over since at least 2016, Charles Leiserson, a computer scientist at MIT, said in the blog. Accordingly, the issue now is to consider how improvements in chip performance fit into a longer-term picture, Willy Shih, an economist at Harvard Business School, said in an explainer.
Reaching atomic levels In that sense, IBM’s latest chip represents an inventive approach for bypassing the limits of physical scaling. Specifically, two wafers with nanosheet-style transistors are glued together like a sandwich to vertically stack two layers of transistors, and related technical assessments suggested that the wafer stacking was flexible and scalable enough to support real computation, Huiming Bu, vice president of IBM’s silicon technology research team, said in a press briefing on the chip. Researcher holding IBM’s sub-1 nm node wafer. Credit: IBM That said, this chip isn’t quite ready for manufacturing just yet. The company’s goal is to enter production in the next five years, but there’s still work to be done. For instance, Bu pointed out that the team was still working on pathways to prevent thermal noise or integration into existing systems in the high-performance computing community. “From my perspective, I hope to see it be as successful as the 2-nanometer [chip] and become the industry platform,” Gambetta said during the briefing. “And as we see with AI and classical computing in general, we are only seeing more and more consumption.” #IBM #Crosses #Computings #Biggest #Barriers #Worlds #Sub1 #Nanometer #ChipIBM,Semiconductors,transistors](https://gizmodo.com/app/uploads/2026/06/nanostacking-ibm-sub-nm-chip-1280x720.jpg "IBM Crosses One of Computing’s Biggest Barriers With World’s First Sub-1 Nanometer Chip
In a major breakthrough, IBM revealed the world’s first semiconductor chip technology built on a sub-1 nanometer chipmaking process. For comparison, the process uses transistor features smaller than the width of a DNA strand, which measures about 2.5 nanometers across. The chip itself is about the size of a fingernail but holds almost 100 billion transistors, and the company expects it could enter markets as early as the next five years. In a statement released today, IBM said the new chip features nearly twice the density of its 2-nanometer chip, released in 2021. According to an accompanying technical report, the chip also demonstrated up to 70% greater energy efficiency than its predecessor. In designing the chip, researchers developed an “entirely new transistor architecture” called nanostack, which “vertically stacks and staggers transistors” to enable IBM’s 0.7-nanometer chip technology, IBM explained. A section of the chip seen with a transmission electron microscope. Credit: IBM “With our new nanostack architecture, we’re not just making smaller transistors,” Jay Gambetta, director of IBM Research, said in the statement. “We’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
Smaller and smaller Semiconductor chips enable things like computers, home appliances, communications, and transportation devices. In 1965, Intel co-founder Gordon Moore surmised that transistor capacities evolved at a predictable and consistent rate. Specifically, all things considered, the number of transistors on a semiconductor chip would double about every two years. For a while, the so-called Moore’s Law held rather well—until, that is, things hit a literal wall.
“Moore’s Law was never meant to last forever,” according to a blog post by the Massachusetts Institute of Technology’s (MIT) Computer Science and Artificial Intelligence Lab. “Transistors can only get so small and, eventually, the more permanent laws of physics get in the way.” That is, as companies try to cram more transistors into smaller chips, new advances in transistor technology take longer than two years, so Moore’s Law has been over since at least 2016, Charles Leiserson, a computer scientist at MIT, said in the blog. Accordingly, the issue now is to consider how improvements in chip performance fit into a longer-term picture, Willy Shih, an economist at Harvard Business School, said in an explainer.
Reaching atomic levels In that sense, IBM’s latest chip represents an inventive approach for bypassing the limits of physical scaling. Specifically, two wafers with nanosheet-style transistors are glued together like a sandwich to vertically stack two layers of transistors, and related technical assessments suggested that the wafer stacking was flexible and scalable enough to support real computation, Huiming Bu, vice president of IBM’s silicon technology research team, said in a press briefing on the chip. Researcher holding IBM’s sub-1 nm node wafer. Credit: IBM That said, this chip isn’t quite ready for manufacturing just yet. The company’s goal is to enter production in the next five years, but there’s still work to be done. For instance, Bu pointed out that the team was still working on pathways to prevent thermal noise or integration into existing systems in the high-performance computing community. “From my perspective, I hope to see it be as successful as the 2-nanometer [chip] and become the industry platform,” Gambetta said during the briefing. “And as we see with AI and classical computing in general, we are only seeing more and more consumption.” #IBM #Crosses #Computings #Biggest #Barriers #Worlds #Sub1 #Nanometer #ChipIBM,Semiconductors,transistors")
![IBM Crosses One of Computing’s Biggest Barriers With World’s First Sub-1 Nanometer Chip
In a major breakthrough, IBM revealed the world’s first semiconductor chip technology built on a sub-1 nanometer chipmaking process. For comparison, the process uses transistor features smaller than the width of a DNA strand, which measures about 2.5 nanometers across. The chip itself is about the size of a fingernail but holds almost 100 billion transistors, and the company expects it could enter markets as early as the next five years. In a statement released today, IBM said the new chip features nearly twice the density of its 2-nanometer chip, released in 2021. According to an accompanying technical report, the chip also demonstrated up to 70% greater energy efficiency than its predecessor. In designing the chip, researchers developed an “entirely new transistor architecture” called nanostack, which “vertically stacks and staggers transistors” to enable IBM’s 0.7-nanometer chip technology, IBM explained. A section of the chip seen with a transmission electron microscope. Credit: IBM “With our new nanostack architecture, we’re not just making smaller transistors,” Jay Gambetta, director of IBM Research, said in the statement. “We’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
Smaller and smaller Semiconductor chips enable things like computers, home appliances, communications, and transportation devices. In 1965, Intel co-founder Gordon Moore surmised that transistor capacities evolved at a predictable and consistent rate. Specifically, all things considered, the number of transistors on a semiconductor chip would double about every two years. For a while, the so-called Moore’s Law held rather well—until, that is, things hit a literal wall.
“Moore’s Law was never meant to last forever,” according to a blog post by the Massachusetts Institute of Technology’s (MIT) Computer Science and Artificial Intelligence Lab. “Transistors can only get so small and, eventually, the more permanent laws of physics get in the way.” That is, as companies try to cram more transistors into smaller chips, new advances in transistor technology take longer than two years, so Moore’s Law has been over since at least 2016, Charles Leiserson, a computer scientist at MIT, said in the blog. Accordingly, the issue now is to consider how improvements in chip performance fit into a longer-term picture, Willy Shih, an economist at Harvard Business School, said in an explainer.
Reaching atomic levels In that sense, IBM’s latest chip represents an inventive approach for bypassing the limits of physical scaling. Specifically, two wafers with nanosheet-style transistors are glued together like a sandwich to vertically stack two layers of transistors, and related technical assessments suggested that the wafer stacking was flexible and scalable enough to support real computation, Huiming Bu, vice president of IBM’s silicon technology research team, said in a press briefing on the chip. Researcher holding IBM’s sub-1 nm node wafer. Credit: IBM That said, this chip isn’t quite ready for manufacturing just yet. The company’s goal is to enter production in the next five years, but there’s still work to be done. For instance, Bu pointed out that the team was still working on pathways to prevent thermal noise or integration into existing systems in the high-performance computing community. “From my perspective, I hope to see it be as successful as the 2-nanometer [chip] and become the industry platform,” Gambetta said during the briefing. “And as we see with AI and classical computing in general, we are only seeing more and more consumption.” #IBM #Crosses #Computings #Biggest #Barriers #Worlds #Sub1 #Nanometer #ChipIBM,Semiconductors,transistors](https://i1.wp.com/gizmodo.com/app/uploads/2026/06/nanostacking-ibm-sub-nm-chip-1280x720.jpg?ssl=1 "IBM Crosses One of Computing’s Biggest Barriers With World’s First Sub-1 Nanometer Chip
In a major breakthrough, IBM revealed the world’s first semiconductor chip technology built on a sub-1 nanometer chipmaking process. For comparison, the process uses transistor features smaller than the width of a DNA strand, which measures about 2.5 nanometers across. The chip itself is about the size of a fingernail but holds almost 100 billion transistors, and the company expects it could enter markets as early as the next five years. In a statement released today, IBM said the new chip features nearly twice the density of its 2-nanometer chip, released in 2021. According to an accompanying technical report, the chip also demonstrated up to 70% greater energy efficiency than its predecessor. In designing the chip, researchers developed an “entirely new transistor architecture” called nanostack, which “vertically stacks and staggers transistors” to enable IBM’s 0.7-nanometer chip technology, IBM explained. A section of the chip seen with a transmission electron microscope. Credit: IBM “With our new nanostack architecture, we’re not just making smaller transistors,” Jay Gambetta, director of IBM Research, said in the statement. “We’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
Smaller and smaller Semiconductor chips enable things like computers, home appliances, communications, and transportation devices. In 1965, Intel co-founder Gordon Moore surmised that transistor capacities evolved at a predictable and consistent rate. Specifically, all things considered, the number of transistors on a semiconductor chip would double about every two years. For a while, the so-called Moore’s Law held rather well—until, that is, things hit a literal wall.
“Moore’s Law was never meant to last forever,” according to a blog post by the Massachusetts Institute of Technology’s (MIT) Computer Science and Artificial Intelligence Lab. “Transistors can only get so small and, eventually, the more permanent laws of physics get in the way.” That is, as companies try to cram more transistors into smaller chips, new advances in transistor technology take longer than two years, so Moore’s Law has been over since at least 2016, Charles Leiserson, a computer scientist at MIT, said in the blog. Accordingly, the issue now is to consider how improvements in chip performance fit into a longer-term picture, Willy Shih, an economist at Harvard Business School, said in an explainer.
Reaching atomic levels In that sense, IBM’s latest chip represents an inventive approach for bypassing the limits of physical scaling. Specifically, two wafers with nanosheet-style transistors are glued together like a sandwich to vertically stack two layers of transistors, and related technical assessments suggested that the wafer stacking was flexible and scalable enough to support real computation, Huiming Bu, vice president of IBM’s silicon technology research team, said in a press briefing on the chip. Researcher holding IBM’s sub-1 nm node wafer. Credit: IBM That said, this chip isn’t quite ready for manufacturing just yet. The company’s goal is to enter production in the next five years, but there’s still work to be done. For instance, Bu pointed out that the team was still working on pathways to prevent thermal noise or integration into existing systems in the high-performance computing community. “From my perspective, I hope to see it be as successful as the 2-nanometer [chip] and become the industry platform,” Gambetta said during the briefing. “And as we see with AI and classical computing in general, we are only seeing more and more consumption.” #IBM #Crosses #Computings #Biggest #Barriers #Worlds #Sub1 #Nanometer #ChipIBM,Semiconductors,transistors")
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