Batteries aren’t magic. They’re chemical. And, like most things built by humans, they wear down over time. I don’t need to tell you this—anyone who has owned a MacBook knows that battery life gets worse and worse as it ages. But what if I told you it’s possible to slow that process down?
One common bit of advice is to only charge your devices up to 80 percent most of the time. Battery University, funded by a consultancy that helps large companies get more out of batteries, suggests this based on its research. So does the National Renewable Energy Laboratory.
But how do you actually follow this advice? The good news is that your MacBook already does this, sort of, and there’s a great free application that allows you to go even further.
Built-In Optimization
Your Mac is designed to only charge up to 80 percent—at least, under some circumstances. By default, Mac devices learn your charging and usage routines and juice up your battery based on that. According to Apple, “Your Mac delays charging past 80 percent when it predicts that you’ll be plugged in for an extended period of time, and aims to fully charge the battery before you unplug.”
What does this mean? Well, for example, if you tend to charge your laptop overnight, your Mac will charge up to 80 percent, then wait until morning to top off the last 20 percent. The idea is to minimize the amount of time the battery is fully charged in a way that you won’t even notice.
The nice thing about this feature is that you don’t have to do anything to look out for your battery’s health. Your Mac is already doing what it can to only charge up to 80 percent whenever your routine suggests it won’t affect you.
(This feature is actually a macOS setting that’s toggled on by default. You can find it in Settings > Battery > Battery Health, where you can toggle this protective setting off, though you should keep reading to figure out if that’s best.)
If you’d rather not think about how charged your battery is, ever again, stop reading. If you want more control, though, I have some advice.
Take Control With a Free App
There are a few potential issues with Apple’s approach. The first is that you’re not in control. You might, for example, discover your MacBook isn’t fully charged if you wake up earlier than usual to catch a flight, and then you’re stuck with a partially charged battery on a long travel day.
For me, though, the bigger issue is that my daily battery usage just isn’t very routine. I do a lot of my work at my desk, where my computer is plugged into my monitor, which also charges it. I like to move around my space throughout the day, though, which means I’m unplugging at random times. And sometimes I put my laptop in my bag and work at the library or a coffee shop. It would be nice to be able to make sure I’m fully charged when I do that.
You get the idea: Not everyone’s routines are predictable. If this sounds familiar, and you’d like to take direct control of your MacBook charging, I recommend the free and open source app named Battery.
This application lives in your menu bar and forces your laptop to only charge up to 80 percent. You can allow full charging at any time, though, by clicking the menu bar icon.
This is going to require a bit of planning and attention on your part. You’re going to have to remember to enable a full charge before you need it, and then turn the limit back on when you know you won’t need it.
But for someone like me, who mostly uses their MacBook at their desk, it feels like a way to ensure my battery stays healthy as long as possible.
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![IBM Crosses One of Computing’s Biggest Barriers With World’s First Sub-1 Nanometer Chip
In a major breakthrough, IBM revealed the world’s first semiconductor chip technology built on a sub-1 nanometer chipmaking process. For comparison, the process uses transistor features smaller than the width of a DNA strand, which measures about 2.5 nanometers across. The chip itself is about the size of a fingernail but holds almost 100 billion transistors, and the company expects it could enter markets as early as the next five years. In a statement released today, IBM said the new chip features nearly twice the density of its 2-nanometer chip, released in 2021. According to an accompanying technical report, the chip also demonstrated up to 70% greater energy efficiency than its predecessor. In designing the chip, researchers developed an “entirely new transistor architecture” called nanostack, which “vertically stacks and staggers transistors” to enable IBM’s 0.7-nanometer chip technology, IBM explained. A section of the chip seen with a transmission electron microscope. Credit: IBM “With our new nanostack architecture, we’re not just making smaller transistors,” Jay Gambetta, director of IBM Research, said in the statement. “We’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
Smaller and smaller Semiconductor chips enable things like computers, home appliances, communications, and transportation devices. In 1965, Intel co-founder Gordon Moore surmised that transistor capacities evolved at a predictable and consistent rate. Specifically, all things considered, the number of transistors on a semiconductor chip would double about every two years. For a while, the so-called Moore’s Law held rather well—until, that is, things hit a literal wall.
“Moore’s Law was never meant to last forever,” according to a blog post by the Massachusetts Institute of Technology’s (MIT) Computer Science and Artificial Intelligence Lab. “Transistors can only get so small and, eventually, the more permanent laws of physics get in the way.” That is, as companies try to cram more transistors into smaller chips, new advances in transistor technology take longer than two years, so Moore’s Law has been over since at least 2016, Charles Leiserson, a computer scientist at MIT, said in the blog. Accordingly, the issue now is to consider how improvements in chip performance fit into a longer-term picture, Willy Shih, an economist at Harvard Business School, said in an explainer.
Reaching atomic levels In that sense, IBM’s latest chip represents an inventive approach for bypassing the limits of physical scaling. Specifically, two wafers with nanosheet-style transistors are glued together like a sandwich to vertically stack two layers of transistors, and related technical assessments suggested that the wafer stacking was flexible and scalable enough to support real computation, Huiming Bu, vice president of IBM’s silicon technology research team, said in a press briefing on the chip. Researcher holding IBM’s sub-1 nm node wafer. Credit: IBM That said, this chip isn’t quite ready for manufacturing just yet. The company’s goal is to enter production in the next five years, but there’s still work to be done. For instance, Bu pointed out that the team was still working on pathways to prevent thermal noise or integration into existing systems in the high-performance computing community. “From my perspective, I hope to see it be as successful as the 2-nanometer [chip] and become the industry platform,” Gambetta said during the briefing. “And as we see with AI and classical computing in general, we are only seeing more and more consumption.” #IBM #Crosses #Computings #Biggest #Barriers #Worlds #Sub1 #Nanometer #ChipIBM,Semiconductors,transistors](https://gizmodo.com/app/uploads/2026/06/nanostacking-ibm-sub-nm-chip-1280x720.jpg "IBM Crosses One of Computing’s Biggest Barriers With World’s First Sub-1 Nanometer Chip
In a major breakthrough, IBM revealed the world’s first semiconductor chip technology built on a sub-1 nanometer chipmaking process. For comparison, the process uses transistor features smaller than the width of a DNA strand, which measures about 2.5 nanometers across. The chip itself is about the size of a fingernail but holds almost 100 billion transistors, and the company expects it could enter markets as early as the next five years. In a statement released today, IBM said the new chip features nearly twice the density of its 2-nanometer chip, released in 2021. According to an accompanying technical report, the chip also demonstrated up to 70% greater energy efficiency than its predecessor. In designing the chip, researchers developed an “entirely new transistor architecture” called nanostack, which “vertically stacks and staggers transistors” to enable IBM’s 0.7-nanometer chip technology, IBM explained. A section of the chip seen with a transmission electron microscope. Credit: IBM “With our new nanostack architecture, we’re not just making smaller transistors,” Jay Gambetta, director of IBM Research, said in the statement. “We’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
Smaller and smaller Semiconductor chips enable things like computers, home appliances, communications, and transportation devices. In 1965, Intel co-founder Gordon Moore surmised that transistor capacities evolved at a predictable and consistent rate. Specifically, all things considered, the number of transistors on a semiconductor chip would double about every two years. For a while, the so-called Moore’s Law held rather well—until, that is, things hit a literal wall.
“Moore’s Law was never meant to last forever,” according to a blog post by the Massachusetts Institute of Technology’s (MIT) Computer Science and Artificial Intelligence Lab. “Transistors can only get so small and, eventually, the more permanent laws of physics get in the way.” That is, as companies try to cram more transistors into smaller chips, new advances in transistor technology take longer than two years, so Moore’s Law has been over since at least 2016, Charles Leiserson, a computer scientist at MIT, said in the blog. Accordingly, the issue now is to consider how improvements in chip performance fit into a longer-term picture, Willy Shih, an economist at Harvard Business School, said in an explainer.
Reaching atomic levels In that sense, IBM’s latest chip represents an inventive approach for bypassing the limits of physical scaling. Specifically, two wafers with nanosheet-style transistors are glued together like a sandwich to vertically stack two layers of transistors, and related technical assessments suggested that the wafer stacking was flexible and scalable enough to support real computation, Huiming Bu, vice president of IBM’s silicon technology research team, said in a press briefing on the chip. Researcher holding IBM’s sub-1 nm node wafer. Credit: IBM That said, this chip isn’t quite ready for manufacturing just yet. The company’s goal is to enter production in the next five years, but there’s still work to be done. For instance, Bu pointed out that the team was still working on pathways to prevent thermal noise or integration into existing systems in the high-performance computing community. “From my perspective, I hope to see it be as successful as the 2-nanometer [chip] and become the industry platform,” Gambetta said during the briefing. “And as we see with AI and classical computing in general, we are only seeing more and more consumption.” #IBM #Crosses #Computings #Biggest #Barriers #Worlds #Sub1 #Nanometer #ChipIBM,Semiconductors,transistors")
![IBM Crosses One of Computing’s Biggest Barriers With World’s First Sub-1 Nanometer Chip
In a major breakthrough, IBM revealed the world’s first semiconductor chip technology built on a sub-1 nanometer chipmaking process. For comparison, the process uses transistor features smaller than the width of a DNA strand, which measures about 2.5 nanometers across. The chip itself is about the size of a fingernail but holds almost 100 billion transistors, and the company expects it could enter markets as early as the next five years. In a statement released today, IBM said the new chip features nearly twice the density of its 2-nanometer chip, released in 2021. According to an accompanying technical report, the chip also demonstrated up to 70% greater energy efficiency than its predecessor. In designing the chip, researchers developed an “entirely new transistor architecture” called nanostack, which “vertically stacks and staggers transistors” to enable IBM’s 0.7-nanometer chip technology, IBM explained. A section of the chip seen with a transmission electron microscope. Credit: IBM “With our new nanostack architecture, we’re not just making smaller transistors,” Jay Gambetta, director of IBM Research, said in the statement. “We’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
Smaller and smaller Semiconductor chips enable things like computers, home appliances, communications, and transportation devices. In 1965, Intel co-founder Gordon Moore surmised that transistor capacities evolved at a predictable and consistent rate. Specifically, all things considered, the number of transistors on a semiconductor chip would double about every two years. For a while, the so-called Moore’s Law held rather well—until, that is, things hit a literal wall.
“Moore’s Law was never meant to last forever,” according to a blog post by the Massachusetts Institute of Technology’s (MIT) Computer Science and Artificial Intelligence Lab. “Transistors can only get so small and, eventually, the more permanent laws of physics get in the way.” That is, as companies try to cram more transistors into smaller chips, new advances in transistor technology take longer than two years, so Moore’s Law has been over since at least 2016, Charles Leiserson, a computer scientist at MIT, said in the blog. Accordingly, the issue now is to consider how improvements in chip performance fit into a longer-term picture, Willy Shih, an economist at Harvard Business School, said in an explainer.
Reaching atomic levels In that sense, IBM’s latest chip represents an inventive approach for bypassing the limits of physical scaling. Specifically, two wafers with nanosheet-style transistors are glued together like a sandwich to vertically stack two layers of transistors, and related technical assessments suggested that the wafer stacking was flexible and scalable enough to support real computation, Huiming Bu, vice president of IBM’s silicon technology research team, said in a press briefing on the chip. Researcher holding IBM’s sub-1 nm node wafer. Credit: IBM That said, this chip isn’t quite ready for manufacturing just yet. The company’s goal is to enter production in the next five years, but there’s still work to be done. For instance, Bu pointed out that the team was still working on pathways to prevent thermal noise or integration into existing systems in the high-performance computing community. “From my perspective, I hope to see it be as successful as the 2-nanometer [chip] and become the industry platform,” Gambetta said during the briefing. “And as we see with AI and classical computing in general, we are only seeing more and more consumption.” #IBM #Crosses #Computings #Biggest #Barriers #Worlds #Sub1 #Nanometer #ChipIBM,Semiconductors,transistors](https://i1.wp.com/gizmodo.com/app/uploads/2026/06/nanostacking-ibm-sub-nm-chip-1280x720.jpg?ssl=1 "IBM Crosses One of Computing’s Biggest Barriers With World’s First Sub-1 Nanometer Chip
In a major breakthrough, IBM revealed the world’s first semiconductor chip technology built on a sub-1 nanometer chipmaking process. For comparison, the process uses transistor features smaller than the width of a DNA strand, which measures about 2.5 nanometers across. The chip itself is about the size of a fingernail but holds almost 100 billion transistors, and the company expects it could enter markets as early as the next five years. In a statement released today, IBM said the new chip features nearly twice the density of its 2-nanometer chip, released in 2021. According to an accompanying technical report, the chip also demonstrated up to 70% greater energy efficiency than its predecessor. In designing the chip, researchers developed an “entirely new transistor architecture” called nanostack, which “vertically stacks and staggers transistors” to enable IBM’s 0.7-nanometer chip technology, IBM explained. A section of the chip seen with a transmission electron microscope. Credit: IBM “With our new nanostack architecture, we’re not just making smaller transistors,” Jay Gambetta, director of IBM Research, said in the statement. “We’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
Smaller and smaller Semiconductor chips enable things like computers, home appliances, communications, and transportation devices. In 1965, Intel co-founder Gordon Moore surmised that transistor capacities evolved at a predictable and consistent rate. Specifically, all things considered, the number of transistors on a semiconductor chip would double about every two years. For a while, the so-called Moore’s Law held rather well—until, that is, things hit a literal wall.
“Moore’s Law was never meant to last forever,” according to a blog post by the Massachusetts Institute of Technology’s (MIT) Computer Science and Artificial Intelligence Lab. “Transistors can only get so small and, eventually, the more permanent laws of physics get in the way.” That is, as companies try to cram more transistors into smaller chips, new advances in transistor technology take longer than two years, so Moore’s Law has been over since at least 2016, Charles Leiserson, a computer scientist at MIT, said in the blog. Accordingly, the issue now is to consider how improvements in chip performance fit into a longer-term picture, Willy Shih, an economist at Harvard Business School, said in an explainer.
Reaching atomic levels In that sense, IBM’s latest chip represents an inventive approach for bypassing the limits of physical scaling. Specifically, two wafers with nanosheet-style transistors are glued together like a sandwich to vertically stack two layers of transistors, and related technical assessments suggested that the wafer stacking was flexible and scalable enough to support real computation, Huiming Bu, vice president of IBM’s silicon technology research team, said in a press briefing on the chip. Researcher holding IBM’s sub-1 nm node wafer. Credit: IBM That said, this chip isn’t quite ready for manufacturing just yet. The company’s goal is to enter production in the next five years, but there’s still work to be done. For instance, Bu pointed out that the team was still working on pathways to prevent thermal noise or integration into existing systems in the high-performance computing community. “From my perspective, I hope to see it be as successful as the 2-nanometer [chip] and become the industry platform,” Gambetta said during the briefing. “And as we see with AI and classical computing in general, we are only seeing more and more consumption.” #IBM #Crosses #Computings #Biggest #Barriers #Worlds #Sub1 #Nanometer #ChipIBM,Semiconductors,transistors")
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